ASSIGNMENT 2: CPU DESIGN
ASSIGNMENT 2: CPU DESIGN
Student Name: Riddhi Patel
Student ID- 2202512
WordCount- 1824
Table of Contents
TOC o "1-3" h z u Introduction PAGEREF _Toc130322780 h 2Design PAGEREF _Toc130322781 h 2Tools and techniques PAGEREF _Toc130322782 h 3Implementation PAGEREF _Toc130322783 h 3Discussion PAGEREF _Toc130322784 h 7Motivation PAGEREF _Toc130322785 h 7Conclusion PAGEREF _Toc130322786 h 8References PAGEREF _Toc130322787 h 10
IntroductionThe design and implementation strategy of a 16-bit RISC central processing unit is the major purpose of this research. The design is conducted with the help of very large-speed integrated circuit hardware description language in the Vivado software. Basically, processors are classified into three categories including 8 bits, 16 bits, and 32 bits. The implementation strategy is dependent on the MIPS architecture to simulate and run the 16-bit processor. In comparison to 8-bit and 32-bit CPUs, 16-bit processors offer greater efficiency and endurance while using less electricity. Various computerized devices, cellular communication, and disc driver controller are only a few examples of 16-bit applications where they are frequently employed. Fixed-length instructions, pipelining, and load-store architecture are all characteristics of RISC processors. There are numerous operations after establishing an architecture of a 16-bit CPU to cover addition, logical functions, subtraction, and multiplication. The envisaged processor has an integrated control unit, memory, ALU, instruction register, program counter, register file, and register file. It is noted that to make description, evaluation, simulation, and implementation easier, all the design modules are VHDL-coded. Hence this section includes design approaches, tools, methodologies, implementation results, further discussions, and any motivation for future aspects.
DesignA microprocessor architecture recognized as RISC is one of the best CPU architecture technology that contains an advanced set of instructions. As per the view of Lowe-Power and Nitta, 2019). It is noted that the 16-bit RISC is a type of non-pipelined architecture-based CPU that has both data memory and instruction memory. It is noted that the RISC processor that has to be made contains 4 categories of pipelining with a 16-bit bus. There are several blocks that can be available in the architecture such as a control unit, arithmetic logical unit, instruction memory, register file, and program counter. The ALU represents various arithmetic operations and bit-shifting functions that should be sued in the architecture of the processor. It is mandatory to use the control unit as a component in the processor design to gain a response to the instructions. These instructions are fetched to the processor to keep some useful information in the architecture. The instructions of the processor need to design with 16-bit widespread with the help of three specific addressing strategies.
As per the view of Zahaf et al. (2020), the design of the digital system needs to be created by synthesizing and implementing the circuit diagram of the processor. The schematic diagram of each component of the processor should be created separately to define the structure of the units.
Tools and techniques
The tools that have been utilized here to design the circuit diagram of a 16-bit central processing unit are considered schematic editor, VHDL programming language, Diligent Basys3 board with a Xilinx Artix 7 FPGA, and Vivado design suite. The implementation of CPU design can be completed by satisfying the placement and routing of the design perfectly. Synthesis is the strategy of converting the RTL design into a logical representation to place and route the netlist in the FPGA machine sources. The basic procedure of the design approach to generate an interactive RISC-based processor are
Install and open the Vivado software and create a project file
Establish a Vivado project file to add sources in that file
Add coding in the VHDL file to create components of the CPU architecture
Run the VHDL code to make a schematic diagram of each element
Simulate the VHDL files to make a circuital diagram of the CPU
Address the 16-bit instructions and overall units to construct the digital system framework
Observe the CPU behavior in the programming task to consider the architectural diagram
Synthesize and implement the project file to generate the entire CPU architecture with all components
As per the view of Cunkas and Ozer, (2019), it is noted that RISC is a step in the technique that sustains a compact and primary set of instructions that all take the same amount of time to execute. This work uses the Verilog HDL to provide a design for a 16-bit RISC processor. The ALU, Controllers, Register files, and Data memory units are the four primary building pieces that make up the RISC processor. The von Neumann architecture was used to implement the suggested CPU, which only has one transmitted memory for data and instructions.
ImplementationThe research approach to develop a digital system by creating a CPU has been comfortably performed in the Vivado tool of the VHDL programming language. The RTL schematic and CPU behavior measurements are analyzed to determine the power estimation of the central processing unit having 16-bit instructions.
Figure 1: Schematic Design of four I/O Ports
(Source: Acquired from Vivado Design Suite)
This picture shows the schematic design of the ports which have been implemented here properly (Xia et al. 2019). The schematic design represents four different encoders and decoders to connect each port to decode the given code.
Figure 2: Schematic Design of the CPU
(Source: Acquired from Vivado Design Suite)
The above figure recognizes the schematic diagram of the 16-bit CPU containing all RTL components. The power consumption of the processor is implemented in the power report section.
Figure 3: 16-bit instructions in RTL components
(Source: Acquired from Vivado Design Suite)
The bit instructions of the RTL component are perfectly analyzed in the Vivado design software application that represents the 16-bit address in the architecture.
Figure 4: CPU behavior schematic diagram
(Source: Acquired from Vivado Design Suite)
The schematic diagram of the CPU behavior is clearly evaluated to define the characteristics of the processor. As per the view of Zhao et al. (2019), the hierarchical design determines the overall features of the CPU to run the behavioral and logical simulation of the design.
Figure 5: Schematic diagram of ALU
(Source: Acquired from Vivado Design Suite)
The schematic design of the arithmetic logical unit delivers the 16-bit address bus of the CPU with clear measurements. These address buses can address various memory locations witty multiple approaches.
Figure 6: Schematic diagram of the control unit
(Source: Acquired from Vivado Design Suite)
The block diagram of the control unit of the processor is designed to get the overall approaches of the instructions. It displays the input and output addresses with a ratio to understand the nature of the central processing unit.
DiscussionThe implementation procedure has been successfully performed in the Vivado software application. It is obvious that developing a CPU having 16-bit instructions is really challenging as it requires lots of knowledge in VLSI design and framework (Buzzi et al. 2020). The analysis of the results provides the actual scenario of the development method with the help of VHD language. It is noticed that a reduced instruction set computer commonly known as RISC is the best design approach to decrease the complexity of the instructions in the CPU. Therefore the implantation of the CPU design has been accurately measured by certain VLSI techniques. The energy consumption, cost, and cycle time have been perfectly balanced from the perspective of CPU design. The design is made on the basis of the logical and arithmetic unit elements to conduct such operations to consume an excessive amount of power (Zhao et al. 2020). The memory of this developed 16-bit processor can be helpful to get addresses from operand1 for delivering them to the instruction decoder.
The RTL schematic has been suitably developed in the software platform after a successful simulation of the existing digital system. The decimal and binary visualization of the processor has also been analyzed to get the arithmetic calculations of the system. As soon as the control units get the Opcode, they produce the signals that instruct the devices and data path to act in the right way and carry out the desired function. Both of the control unit's instruction decoders are present in the 16-bit processor that has been constructed in the proposed software. As per the view of Dezordi et al. (2022), the signal is sent through an ALU, a universal shift register, or a barrel shift rotator after these two decoders have decoded the instruction bits.
MotivationThere are some major benefits to creating a developed architectural diagram of a 16-bit processor in the Vivado software application. It is necessary to know the fact behind developing this design as it generates lower costs than 32-bit processors. The usage of transistors and manufacturer cost is very lower in the internal data paths of that processor. The external memory of the processor employs 16-bit paths and a low level of complexity provides a motivational perspective to establish a 16-bit CPU by using the VHDL programming strategy. The FPGA applications can be more accurate in the future by generating this CPU architecture (Zhao et al. 2021). It is essential to understand the basic criteria before starting this approach to accomplish creative solutions by inventing a central processing unit. There are some impactful benefits of the VHD language to preparing structural farmwork of the 16-bit central processing unit. The analysis of the overall outcomes of that processor design approach can manage all types of operations. It is understood that the advanced concepts behind the VHDL are
Effective in a large number of design principles
Flexible in VLSI design
Appropriate in design management segment
Supportive for all kinds of CAD tools
Supportive in multi-level abstraction
Effective in code sharing as well as reusability
It is observed that the performance of the 16-bit microprocessor is really greater than all other microprocessors as memory advantage is quite advanced in these processes (Zhu et al. 2020). Due to the single cycle in a 16-bit machine, a CPU can perform more activities than other processors in the exact cycle.
ConclusionIn conclusion, this part of the study gives students a chance to design digital systems and expand their understanding of the VHDL programming language. On the Digilent Basys3 board with a Xilinx Artix 7 FPGA, the VHDL code has been utilized to implement a 16-bit CPU for this task. A digital system design has been implemented, synthesized, and downloaded to target hardware, tested, debugged, and verified to meet specifications. Modular coding is highly recommended because it increases modularity, flexibility, maintainability, and reusability. For sequential circuits, the following code should use sequential codes and parallel instructions for combinatorial circuits. The task is required to implement a 16-bit CPU with a program sequence/control flow instruction datapath and an arithmetic/logic instruction datapath in accordance with the design specification. The CPU's required instruction opcodes are listed in the table. Additionally, the control unit must incorporate a decode unit to interpret the "effects" and control signals derived from each instruction's output. In conclusion, the second course provides taking the CE869 with a stimulating and challenging opportunity to enhance the understanding of the VHDL language and design digital systems. Through this study, anyone gains hands-on experience implementing a digital system design, testing, debugging, validating, and implementing a 16-bit CPU.
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