Design a keypad lock with 4-digit access code - 2337. The keypad is designed as below, with numbers 0-9 and ENTER (E) and CLEAR (C) buttons. To unlo

Design a keypad lock with 4-digit access code - 2337. The keypad is designed as below, with numbers 0-9 and ENTER (E) and CLEAR (C) buttons. To unlock the door, the right sequence of buttons must be pressed, followed by the ENTER button. Pressing the CLEAR button will reset the entered sequence. If an incorrect code is entered 3 times in a row, an alarm must sound (until a reset is applied).

The lock should take input from a keypad (K[11:0] in the diagram above) and should produce two outputs lock and alarm. If the correct sequence is entered, lock should be LOW for 3 clock cycles, to allow the user to enter. Additionally, there should be reset and clk inputs. You can assume that the keypad is only pressed whilst the clock is high, and is always released when the clock is low, and furthermore that neither of these events will occur on an edge of the clock (i.e. your input is stable around the clock edges).

For your assignment, you need to

1. Identify the system inputs and outputs.

2. Draw a state diagram for the FSM.

3. Determine if the number of states can be reduced and assign them with binary codes.

4. Design and implement the FSM using D, T and JK flip-flops.

5. Write Verilog HDL models for:

a. The machine based on the state diagram in (2) (behavioural modelling)

b. The JK flip-flop sequential circuit that you implement in (4) (structural or dataflow modelling)

6. Verify the HDL models in (5).

7. Your design for each question should aim at achieving optimized implementation. It should include your design procedure, choice of technology implementation, and simulation results. The gate input cost must be also calculated. Use Xilinx ISE to simulate and verify your design.

Report Submission:

This should contain:

Completed and signed assignment submission form as the front page

State diagram

Implementation

Verilog HDL code (screenshots or text)

Verilog testbenches (screenshots or text)

ISim simulation results (screenshots)

In addition to the report you must also submit all your Verilog modules (excluding testbenches) as separate files. As we will be running an autotest script on your code, you will need to use the following structure:

Behavioural Model: Your top-level module must be named ass2_behavioural and must have the following port names (If these do not exactly match then your design will fail the autotests, order doesnt matter):

Inputs: clk, reset, keypad[11:0]

Outputs: lock, alarm

Structural/Dataflow Model: Your top-level module must be named ass2_structural and must have the following port names (If these do not exactly match then your design will fail the autotests, order doesnt matter):

Inputs: clk, reset, keypad[11:0]

Outputs: lock, alarm